1. Field of the Invention
The present invention generally relates to microprocessors, and more particularly to a microprocessor having the function of prefetching an instruction. 2. Description of Related Technology
Nowadays, microprocessors are widely used in various electronic devices. Generally, a microprocessor has an interrupt function in which an interrupt process is generated when the microprocessor executes a predetermined address. This predetermined address is detected by an interrupt generating device located outside of the microprocessor, and an interrupt indication (signal) is applied to the microprocessor when the predetermined address is detected.
There is also known a microprocessor having the prefetch function in addition to the interrupt function. In such a microprocessor, the address at which the interrupt process is generated may not be executed. In this case, the interrupt occurs at an address which has not been actually executed.
The above event will now be described with reference to the following table.
______________________________________ Address Instruction Operand ______________________________________ 1000 mov r0, r1 1002 add r2, r3 1004 beq 1200 1006 mov r3, r0 1008 add r4, r5 ______________________________________
The instruction stored at address #1006 may be executed due to the presence of a conditional branch instruction "beq (branch equal)" stored at address #1004 immediately preceding address #1006.
However, in the microprocessor having the prefetch function, the instruction that is stored at address #1006 and has not been actually executed is prefetched. In this case, there is a problem such that the interrupt signal is supplied to the microprocessor due to the address detection performed outside of the microprocessor, and the interrupt process takes place with respect to the address which has not been executed.
There is another problem, which will be described by referring to FIGS. 1A-1B. The external interrupt generating device detects the predetermined address and generates the interrupt signal. In this case, the interrupt does not occur in the same cycle as the address detection, but occurs with a one-cycle delay caused by a factor such as a delay in the interrupt generating device. For example a target cycle for interrupt is indicated at (a) and a cycle in which interrupt actually occurs is indicatedat (b).